This invention generally relates to mathematical function processing units for data processing. This invention more particularly pertains to a square root processing unit and to a division processing unit.
With a view to achieving high speed computation, the computer industry is continuously trying to provide improved mathematical function processing units. Conventionally, when finding a mathematical function of one or more variables, a part of a value of a certain variable is used as an address to retrieve, from a large-capacity table information store unit, either a function initial value or a numeric value used during the course of calculation whereby high speed computation is accomplished using the retrieved value.
U.S. Pat. No. 5,278,782, granted Jan. 11, 1994 to H. Nakano, shows a square root operation device. This device uses a table information store unit for storing an approximation of the reciprocal of a square root (hereinafter referred to as "ARSQR"). A search through the table information unit is made as follows. When handling a fixed-point number operand, the fixed-point number operand is normalized in units of two bits, and N bits following the head of the normalized operand are used as an address to search through the table information store unit to find an ARSQR. The number N is a plus integer greater than or equal to three. On the other hand, when handling a floating-point number operand with an exponential radix of 2, if an exponent, with bias removed, is odd, a mantissa is shifted to the left too far by one bit place in comparison with an even exponent, and N bits of the resulting mantissa are used as an address to search through the table information store unit to find an ARSQR. This square root operation device further includes a carry look ahead circuit for performing rounding operations on partial square roots, to accomplish high-speed computation. If a portion lower than a least significant bit (LSB) of a partial square root is greater than or equal to a half quantity of that LSB, then rounding-up is automatically done, regardless of the number of times an iterative operation is carried out.
U.S. Pat. No. 5,065,352, granted Nov. 12, 1991 to H. Nakano, discloses a divide apparatus. This divide apparatus has a table information store unit for storing an approximation of the reciprocal of a divisor (hereinafter referred to as "ARD". A fixed-point number operand is converted into an absolute value representation. This converted operand is then bit-normalized and N bits following a most significant bit of the normalized operand are extracted to serve as an address to search through the table information store unit to find an ARD. The number N is a plus integer. When handling a floating-point number operand, a mantissa of an operand is extracted, bit normalization is carried out, and N bits are extracted to serve as an address to search through the table information store unit to find an ARD.
The above-described U.S. Pat. No. 5,278,782 device, however, has some drawbacks. For example, there is a difference in ARSQR precision between a case where top 2 bits of a post-normalization fixed-point number operand are 01 and a case where they are 10 or 11. The former case suffers from lower ARSQR precision than the latter case. Additionally, in the case of the floating-point number operand, a similar problem arises. In other words, there also exists a difference in ARSQR precision between a case where top 2 bits of a mantissa are 01 (i.e., where an exponent, with bias removed, is even) and a case where they are 10 or 11 (i.e., where an exponent, with bias removed, is odd). The former case suffers from lower ARSQR precision than the latter case. Further, regardless of the number of times an iterative calculation is executed, rounding-up is executed if a portion lower than a least significant bit (LSB) of a partial square root is greater than or equal to a half quantity of that LSB. This produces a problem. That is, the position of taking an upper partial square root of a product of a partial remainder by an ARSQR is moved to the left one bit place in each iterative calculation following the first iterative calculation. As a result, a carry propagation bit from the carry look ahead circuit to the rounder/adder for calculating partial square roots is likewise moved to the left one bit place in each iterative calculation following the first iterative calculation. Therefore, the operation of the carry look ahead circuit in the first iterative calculation differs from the operation of the carry look ahead circuit in each iterative calculation following the first iterative calculation.
The above-described U.S. Pat. No. 5,065,352 device has some disadvantages. For example, there is a difference in ARD precision between a case where a head bit of an address lower by one bit place than a most significant bit of a bit-normalized operand is 0 and a case where it is 1. In other words, the former case suffers from lower ARD precision than the latter case.